VILLASfpga
VILLASfpga is an extension to VILLASnode for hard real-time / FPGA-supported simulation. For local real-time co-simulations, VILLASfpga provides an FPGA-based hard real-time interconnect to couple simulators and HIL testbenches. VILLASfpga consists of a reconfigurable cross-bar switch to adjust signal routing during runtime and provides DMA engines for data transfer to the VILLASnode software gateway.
Architecture
Documentation
We provide user documentation on this website: https://villas.fein-aachen.org/docs/fpga/.
For further question please consider joining our Slack channel: FEIN Aachen e.V. Slack.
Publications
VILLASfpga is presented and/or used by the following publications.
We kindly ask acadmic users of our tools to cite the following paper in their own publications.
- S. Vogel, “Development of a modular and fully-digital PCIe-based interface to Real-Time Digital Simulator,” M.S. Thesis, Institute for Automation of Complex Power Systems, RWTH Aachen University, Aug-2016.
Also check the list of publications of VILLASframework.
Slides
- VILLASfpga (Master Thesis defense - Steffen Vogel - 20th July 2016 - Aachen, Germany)
Downloads
For details please consult the Downloads page.
Copyright
2018, Institute for Automation of Complex Power Systems, EONERC
Licensing
VILLASfpga is currently closed-source due to propietary firmware components which we can not share. Please contact Steffen Vogel for details.
Other licensing options available upon request. Please contact Prof. Antonello Monti for further details.
Contact / Mailing list
The project is using a public mailing list for announcements and general discussions. Please click on the link above to subsribe.
- Steffen Vogel (post@steffenvogel.de)
- Daniel Krebs (dkrebs@eonerc.rwth-aachen.de)
Institute for Automation of Complex Power Systems (ACS) EON Energy Research Center (EONERC) RWTH University Aachen, Germany